Field of the Invention
The invention lies in the field of semiconductor circuit technology and it pertains, more specifically, to a system for testing fast synchronous semiconductor circuits, particularly semiconductor memory chips, in which test signals such as test data, control, address and timing reference or clock signals (DQ, DQS, addr, cmd, clk_out) are generated on the basis of signal conditions input by the testing device, supplied to the circuit to be tested and evaluated by the latter in dependence on response signals generated by the test signals. A timing reference circuit is provided for generating timing reference signals, the phase angle of which can be programmed, as timing reference for the test signals to be generated and the response signals from the semiconductor circuit to be tested, which are to be evaluated.
A test system of that type is known from U.S. Pat. No. 6,032,282 (see also German published patent application DE 195 34 735 A1). Modern DRAM (Dynamic Random Access Memory) chips are tested by means of costly production testing device. The latter allow signals having precisely defined voltage levels to be applied to the memory chip or DUT (Device Under Test) to be tested at precisely defined times. During the checking of the read function of the DUT, it is also possible to read signals coming from the DUT into the test equipment at precisely defined times and to compare them with expected signal values.
Due to the high frequencies of current memory chips, such as, for example, 400 megahertz clock frequency in the case of Rambus DRAMs, the specification of these chips requires a high timing accuracy of the signals (in the case of DDR (Double Data Rate) memories, signal specifications of the order of magnitude of 500 ps are already currently used). For this reason, production testing devices must in some cases meet the highest technical requirements which leads to correspondingly high costs. Current DRAM production test equipment cost several million dollars. For this reason, the costs of testing extremely high frequency memory chips already amount to up to 30% of the total production costs.
At present, no proposal for testing fast SGRAM or DRAM memory chips is known which, using low-frequency, more inexpensive production test equipment hitherto used, would, nevertheless, provide a highly accurate measurement of the signals read out of a DUT. Memories are still being tested in the traditional way by means of highly complex and expensive production test equipment. Known production test equipment provides a large number of independent input/output channels which are generally freely programmable individually. The various input/output channels are compared relative to an internal timing reference of the testing device and with data patterns generated in the testing device. For this reason, the various input/output channels are driven with numerous ASIC chips and electronic components via complex pin cards.
U.S. Pat. No. 6,032,282 describes a clock edge shaping circuit for use in an IC test system. In that system, a pattern generating device provides test patterns on the basis of signal conditions input by a testing device for a clock signal to be supplied to a circuit to be tested, the front and back edge of which signal can be shaped programmably by the prior art clock edge shaping circuit. Response signals generated in dependence on the test signals are evaluated. It is thereby also possible to synchronize the expected patterns for a comparison with the signals obtained from a tested chip. It must be emphasized that the clock edge shaping circuit known from the published document is used in semiconductor IC test equipment and is not a component of an additional semiconductor chip which is inserted into the signal path between test equipment and a semiconductor chip to be tested or DUT.
Japanese published patent application JP 05-264,667 A describes a test circuit which receives a slow clock signal CKT and generates from this a high-speed clock signal by means of a frequency multiplier. In this arrangement, slow test data are converted into fast test data by means of selectors, parallel-serial converters and multiplexers, and are output to a circuit operating at high clock frequency. The result data of this circuit are converted into slow output data by means of multiplexers, serial/parallel converters and selectors. The test circuit known from this printed document is integrated in a LSI circuit and, accordingly, does not form a separate semiconductor circuit chip which is inserted between test equipment and a semiconductor circuit to be tested and is spatially associated with the semiconductor circuit to be tested.
It is accordingly an object of the invention to provide a system for testing fast synchronous semiconductor circuits, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which test system, in particular, is designed for a test of high-frequency DRAMs, in such a manner that the hitherto complicated DUT interface and other components can be greatly simplified or, respectively, reduced, that the functions according to the invention can be implemented in a single semiconductor chip, and that the more inexpensive production test equipments hitherto used can still be used.
With the foregoing and other objects in view there is provided, in accordance with the invention, a system for testing fast synchronous semiconductor circuits, in particular semiconductor memory chips. The system comprises:
a testing device connected via a signal path to a semiconductor circuit to be tested, wherein the semiconductor circuit to be tested is connected to receive test signals selected from the group consisting of test data signals, control signals, address signals and timing reference and clock signals generated in dependence on signal conditions defined by the testing device, and wherein the semiconductor circuit to be tested generates response signals in response to the test signals; and
a semiconductor circuit chip connected in the signal path between the testing device and the semiconductor circuit to be tested and spatially associated with the semiconductor circuit to be tested, the semiconductor circuit chip containing a timing reference circuit for generating timing reference signals with a programmable phase angle and forming a timing reference for the test signals and the response signals, and circuits for generating the test signals and for evaluating the response signals received from the semiconductor circuit being tested.
In other words, the objects are achieved with a test system with a separate semiconductor chip (BOST chip), which is spatially associated with the semiconductor circuit to be tested, is inserted into the signal path between the test equipment and the semiconductor circuit to be tested and contains the timing reference circuit and circuit means for generating the test signals and for evaluating the response signals from the semiconductor circuit to be tested.
In this configuration, a clock signal used by the timing reference circuit for generating the timing reference signals can be generated either internally by a clock generator located in the BOST chip or derived from a highly accurate basic clock signal generated externally.
In the BOST chip, first controllable transmit driver and receiver elements for data words which are written to the DUT by the BOST chip and data words which are read out of the DUT by the BOST chip are provided and the timing of these first controllable transmit driver and receiver elements can be controlled by a first and a second timing reference signal which is in each case generated by the timing reference circuit.
The BOST chip also has second controllable transmit driver elements for addresses and command signals to be sent to the DUT, and the timing of the second transmit driver elements can be controlled by a third timing reference signal generated by the timing reference circuit. Furthermore, third controllable transmit driver and receiver elements for data strobe signals which are written to the DUT by the BOST chip and data strobe signals which are read out of the DUT by the BOST are provided in the BOST chip. The timing of these third transmit driver and receiver elements can be controlled by a fourth timing reference signal generated by the timing reference circuit.
The timing reference circuit preferably and advantageously has a first DLL circuit (delay-locked loop circuit) with programmable delay.
For this purpose, storage registers can be provided in the BOST chip, in each case for storing a programming value for programming the delay of the DLL circuit. These storage registers can be preferably loaded with a start or base value by the test equipment.
Since the timing of the data words read out of the DUT by the BOST chip and received by the receiver elements is specified with respect to the clock signal supplied to the DUT by the BOST chip, the clock signal generated by the BOST chip and output to the DUT is preferably picked up by a signal tap close to the DUT and fed back to the DLL circuit in the BOST chip by means of circuit means so that the correct arrival in time of the data word signals at the BOST chip is measured with maximum accuracy with respect to the clock signal fed back, by means of this feedback of the timing reference which has the same development in time as the data words read from the DUT. For this purpose; a second delay-locked loop circuit DLL is connected to the clock signal fed back in the BOST chip. This DLL circuit allows a programmable delay signal to be generated for latching in, accurately timed, the data word response signals from the DUT received from the DUT by the first receiver elements.
With the BOST concept, the proposed test system provides for an inexpensive solution since a BOST chip containing the functional units necessary for implementing the proposed test system can be produced very inexpensively in comparison with the high costs of current highly accurate production test equipments and provides for placement close to the DUT which makes for higher accuracy of the test.
It should be noted that the test system according to the invention with the proposed BOST solution is not only suitable for testing very fast synchronous DRAM and SGRAM chips in single-data-rate (SDR) mode or in double-data-rate (DDR) mode but also for testing other synchronous digital semiconductor circuits since the proposed concept provides for the highly accurate measurement of data signals on the basis of the timing reference signals generated in the BOST.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a system for testing fast synchronous semiconductor circuits, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.